Программирование для встроенных систем - статьи

       

Литературааа


  1. E. Lee. Programmable DSP Architectures: Part I. IEEE ASSP Magazine, pp 4-19, October 1988.
  2. E. Lee. Programmable DSP Architectures: Part II. IEEE ASSP Magazine, pp 4-14, January 1989.
  3. S. Davidson, D. Landskov, B.D. Shriver, P.W.Mallett. Some Experiments in Local Microcode Compaction for Horizontal Machines. IEEE Trans. on Computers, vol. 30, no. 7, 1981, pp. 460-477
  4. Khalid Ismail. DSP Architecture Implications on Compilation.
  5. Richard M. Stallman. Using and Porting the GNU Compiler Collection.
  6. Ashok Sudarsanam. Code Optimization Libraries For Retargetable Compilation For Embedded Digital Signal Processors
  7. C. Liem. Retargetable Compilers for Embedded Core Processors. Kluwer Academic Publishers, 1997
  8. Алла Солонина, Дмитрий Улахович, Лев Яковлев. Алгоритмы и процессоры цифровой обработки сигналов. БХВ-Петербург, 2001
  9. Vasanth Bala, Norman Rubin. Efficient Instruction Scheduling Using Finite State Automata. 1995
  10. P. Briggs. Register Allocation via Graph Coloring. PhD Thesis, RICE University, 1992
  11. M. Saghir, P. Chow, C. Lee. Exploiting Dual Data-Memory Banks in Digital Signal Processors. In Proceedings of the ACM SIGARCH Conference on Architectural Support for Programming Languages and Operating Systems, 1996
  12. Rainer Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, 1997
  13. S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang. Storage Assignment to Decrease Code Size. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 186-195, June 1995


  14. R. Leupers, P. Marwedel. Algorithms for Address Assignment in DSP Code Generation. In Proceedings of the International Conference on Computer-Aided Design, 1996
  15. Шумаков С.М. Обзор методов оптимизации кода для процессоров с поддержкой параллелизма на уровне команд. сентябрь 2003, http://www.citforum.ru/programming/digest/20030430/
  16. V. Allan, R. Jones, R. Lee, S. Allan. Software Pipelining
  17. B. Ramakrishna Rau. Iterative Modulo Scheduling: An Algorighm For Software Pipelining Loops



  18. A. Aiken, A. Nicolau, S. Novack. Resource-Constrained Software Pipelining.


  19. T. Proebsting, C. Fraser. Detecting Pipeline Structural Hazards Quickly. 1994


  20. Rainer Leupers. Code Optimization Techniques for Embedded Processors. Kluwer Academic Publishers, 2000


  21. R. Ramakrishna Rau. Iterative Modulo Scheduling: An Algorithm For Software Pipelining Loops


  22. G. Araujo, S. Malik. Optimal Code Generation for Embedded Memory Non-Homogeneous Register Architectures. 1995


  23. R. Leupers. Register Allocation for Common Subexpressions in DSP Data Paths. 2000


  24. R. Leupers, P. Marwedell. Retargetable Compiler Technology for Embedded Systems.


  25. R. Leupers, S. Bashford. Graph based Code Selection Techniques for Embedded Processors.


  26. M. Wallace, S. Novello, J. Schimpf. ECLiPSe: A Platform for Constraint Logic Programming.


  27. V. Zivonovich, J.M. Velarde, C. Schläger, H. Meyr. DSPStone – A DSP-oriented Benchmarking Methodology. 1994


  28. S. Bashford, R.Leupers. Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. 1999



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